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The Impact of BTI Variations on Timing in Digital Logic Circuits

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2 Author(s)
Jianxin Fang ; Department of Electrical and Computer Engineering, University of Minnesota, Minneapolis, MN, USA ; Sachin S. Sapatnekar

A new framework for analyzing the impact of bias temperature instability (BTI) variations on timing in large-scale digital logic circuits is proposed in this paper. This approach incorporates both the reaction-diffusion model and the charge-trapping model for BTI and embeds these into a temporal statistical static timing analysis framework capturing process variations and path correlations. Experimental results on 32-, 22-, and 16-nm technology models, which were verified through Monte Carlo simulation, confirm that the proposed approach is fast, accurate, and scalable and indicate that BTI variations make a significant contribution to circuit-level timing variations.

Published in:

IEEE Transactions on Device and Materials Reliability  (Volume:13 ,  Issue: 1 )