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A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS

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4 Author(s)
Pei-Yao Chang ; Department of Electrical Engineering and SoC/AIM-HI centers, National Chung Cheng University (CCU), Taiwan ; Tay-Jyi Lin ; Jinn-Shyan Wang ; Yen-Hsiang Yu

This brief presents a 4R/2W register file design for two-issue microprocessors with ultra-wide dynamic voltage scaling. A full-N separated read port has been proposed to save ~ 19% area and to improve 4.5 ~ 10.4 % performance of state-of-the-art 1P3N designs for subthreshold operations. In addition, a reconfigurable write scheme has been proposed to utilize the unused write port in the energy-efficient mode with single-issue execution for ~ 18% write noise margin improvement. A test chip has been designed and fabricated using the TSMC 65-nm GP process, of which a minimum operating voltage of 148 mV has been measured.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:59 ,  Issue: 12 )