By Topic

A 4R/2W Register File Design for UDVS Microprocessors in 65-nm CMOS

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Pei-Yao Chang ; Dept. of Electr. Eng. & SoC/AIM-HI Centers, Nat. Chung Cheng Univ. (CCU), Chiayi, Taiwan ; Tay-Jyi Lin ; Jinn-Shyan Wang ; Yen-Hsiang Yu

This brief presents a 4R/2W register file design for two-issue microprocessors with ultra-wide dynamic voltage scaling. A full-N separated read port has been proposed to save ~ 19% area and to improve 4.5 ~ 10.4 % performance of state-of-the-art 1P3N designs for subthreshold operations. In addition, a reconfigurable write scheme has been proposed to utilize the unused write port in the energy-efficient mode with single-issue execution for ~ 18% write noise margin improvement. A test chip has been designed and fabricated using the TSMC 65-nm GP process, of which a minimum operating voltage of 148 mV has been measured.

Published in:

Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 12 )