Flash ADC Comparators and Techniques for Their Evaluation

We have designed three flavors of a periodic comparator to minimize its phase-dependent nonlinearities. One flavor uses a differential “quasi-one-junction” SQUID (DQOS) quantizer with a low-inductance clocking scheme. The second flavor uses a differential SQUID wheel quantizer, and the third flavor uses a symmetric differential SQUID wheel quantizer with time-interleaved clocks. We also describe a different common mode biasing scheme that gates the quantized signal to apply full signal during the clock aperture, and an attenuated signal outside the clock aperture. We also developed a new performance analysis scheme based on sweeping the dc offset of a single periodic comparator during beat frequency test while following the position of its threshold, which yield both signal reconstruction and duty cycle of the comparator. Using this, we discovered the dependence of the sensitivity of the comparator duty cycle to its dc bias and the slew rate of the signal. This shows a reduction in the effective current amplitude seen by the sampler at increasing slew rates while the quantizer current does not change, indicating a potential performance reduction mechanism arising from finite regeneration time of a clocked comparator that prohibits it from conclusively resolving the polarity of a rapidly oscillating input signal. We also report experimental measurement results for the three flavors of the comparator. Both DQOS and differential SQUID wheel comparators exhibited 4 bits of Gray (3 bits of binary) code resolution for a 20-GHz beat frequency test; 1-bit more than previously demonstrated performance. For a 15 GHz beat frequency, each symmetric differential SQUID wheel time-interleaved comparator exhibited 4.3 bits of resolution. We also demonstrate threshold interleaving of two DQOS comparators to get 4.5 effective bits for a 20-GHz beat frequency test.