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Time-based power control architecture for application processors in smartphones

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3 Author(s)
Kim, S.-Y. ; Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol. (POSTECH), Pohang, South Korea ; Koo, K. ; Kim, S.W.

Proposed is an architecture for reducing the power consumption of an application processor (AP) in a smartphone. The proposed architecture is designed for sharing the main memory between the AP and modem blocks. A power-saving algorithm is proposed that focuses on random and sparse data patterns in connected and idle modes. The algorithm automatically performs power/clock gating without the intervention of the CPU, unlike dynamic voltage and frequency scaling. To control power gating, a power consumption model is formulated to solve an optimisation problem. The proposed algorithm is verified with electronic system level simulation based on actual scenarios of a mobile terminal. The results show an improvement in power consumption.

Published in:

Electronics Letters  (Volume:48 ,  Issue: 25 )

Date of Publication:

December 6 2012

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