Skip to Main Content
A low-voltage, current-reused, quadrature voltage controlled oscillator (QVCO) and divide-by-4 frequency divider (FD4) architecture is presented for the first time. The proposed architecture features compact and low voltage operation by the proper stacking of a ring-type injection locked FD4 and a back-gate coupled QVCO. This design lowers the power consumption and eliminates the need of high frequency divider as well as buffering stage. The circuit has been implemented in 0.18-μm triple-well CMOS process. Experimental results show a phase noise level of -114.1 dBc/Hz at 1 MHz offset from carrier (2.2 GHz). This chip occupies a core area of 0.9×0.35 mm2 and consumes 2.7 mA from a 1.3 V power supply.
Date of Publication: Feb. 2013