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A 0.016-mm2 144-μ W three-stage amplifier capable of driving 1-to-15-nF capacitive load (CL) is described. It is optimized via combining current-buffer Miller compensation and parasitic-pole cancellation (via an active left-half-plane zero circuit) to extend the CL drivability with small power and area. Fabricated in 0.35-μ m CMOS, the minimum gain-bandwidth product (GBW), slew rate (SR) and phase margin measured over 1-to-15-nF CL are 0.95 MHz, 0.22 V/ μs and 52.3 °, respectively. The results at 15-nF CL correspond to 2.02x-improved small-signal FOMS (=GBW·CL/Power), and 1.44x-improved large-signal FOML (=SR·CL/Power) with respect to prior art. The sizing and optimization are systematically guided by Local Feedback Loop Analysis. It is an insightful control-centric method allowing the pole-zero placements to be more analyzable and comparable at the system level.
Date of Publication: Feb. 2013