By Topic

A 28nm 6T SRAM memory compiler with a variation tolerant replica circuit

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Sharad Gupta ; External Dev. & Manuf. (EDM), Texas Instrum. India Pvt. Ltd., Bangalore, India ; Parvinder Kumar Rana

We propose an SRAM replica tracking circuit that reduces divergence of the replica path relative to normal read path (6-16% less Sense differential Requirement), thus improving the access time by 5-8%. The approach is compatible to power managed SRAMs having Retain till Access feature and also for non power managed SRAMs with no sense differential impact. Using This Replica tracing circuit Sense differential has been well tracked across all array and periphery voltages combinations which further improve the access time by 4-6%. Instances with this method 0.5-256Kb have been tested on a 28nm CMOS LP process.

Published in:

SoC Design Conference (ISOCC), 2012 International

Date of Conference:

4-7 Nov. 2012