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A template-based methodology for efficient microprocessor and FPGA accelerator co-design

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5 Author(s)
Kritikakou, A. ; Dept. Electr. & Comput. Eng., Univ. of Patras, Patras, Greece ; Catthoor, F. ; Athanasiou, G.S. ; Kelefouras, V.
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Embedded applications usually require Software/Hardware (SW/HW) designs to meet the hard timing constraints and the required design flexibility. Exhaustive exploration for SW/HW designs is a very time consuming task, while the adhoc approaches and the use of partially automatic tools usually lead to less efficient designs. To support a more efficient codesign process for FPGA platforms we propose a systematic methodology to map an application to SW/HW platform with a custom HW accelerator and a microprocessor core. The methodology mapping steps are expressed through parametric templates for the SW/HW Communication Organization, the Foreground (FG) Memory Management and the Data Path (DP) Mapping. Several performance-area tradeoff design Pareto points are produced by instantiating the templates. A real-time bioimaging application is mapped on a FPGA to evaluate the gains of our approach, i.e. 44,8% on performance compared with pure SW designs and 58% on area compared with pure HW designs.

Published in:

Embedded Computer Systems (SAMOS), 2012 International Conference on

Date of Conference:

16-19 July 2012