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A 3 Megapixel 100 Fps 2.8 \mu m Pixel Pitch CMOS Image Sensor Layer With Built-in Self-Test for 3D Integrated Imagers

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3 Author(s)
Shang-Fu Yeh ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chih-Cheng Hsieh ; Ka-Yi Yeh

This paper presents a 3 megapixel 100 fps 2.8 μm pixel pitch CMOS image sensor (CIS) layer with built-in self-test (BIST) for three-dimensional (3D) integrated imagers. A modular CIS sub-array is proposed with new readout and control scheme. It needs only one micro-bump (μbump) per sub-array, instead of per-pixel or per-column, to release the design rule restriction of the 3D stacking process. The proposed readout structure with in-pixel two-dimensional (2D) decoding function achieves high spatial resolution, without degrading the frame rate. A BIST circuit is also proposed to filter out unqualified CIS layer before chip stacking, improving the yield performance of the final 3D integrated imagers, without adding extra transistor in the pixel. A CIS chip with 16 × 8 sub-arrays and a pixel size of 2.8 × 2.8 μm2 was fabricated in TSMC 0.18 μm CIS process. The experimental results demonstrate the successful parallel output images of 3 megapixels with 16 × 8 modules at 100 fps. This shows that the imaging resolution is expandable by the proposed modular sub-array design and is expected to achieve 100 fps at multi-mega imaging for high-speed HDTV camera applications.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:48 ,  Issue: 3 )