We have systematically studied the passivation of InP (100) and (111)A substrate using atomic-layer-deposited Al2O3 as gate dielectric. Modified high- and low-frequency method and full conductance method has been applied to evaluate the interface trap density (Dit) distribution at Al2O3/InP interface through MOS capacitor (MOSCAP) and MOSFET measurements. Lower Dit towards conduction band is obtained from (111)A surface, accompanied by an increase in midgap Dit. This leads to the demonstration of record-high drive current (Ids=600 μA/μm) for a InP (111)A NMOSFET with gate length (LG) of 1 μm and relatively large subthreshold swing of 230 mV/dec at off-state. Detailed DC IV and current drift measurements confirm the trap distribution from capacitance-voltage characterization. A trap neutral level (E0) model is proposed to explain all observations from MOSCAP and MOSFET characterizations. A universal behavior of the E0 shift on III-V (111)A surface is also analyzed and this observation can play a pivotal role in interface engineering for future III-V CMOS technology with 3D structures.