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High-performance low-power sensing scheme for nanoscale SRAMs

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2 Author(s)
A. Valaee ; Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, QC, Canada ; A. J. Al-Khalili

SRAMs in nanoscale CMOS technology suffer from plethora of design challenges such as increased process variation, increased leakage current and variation in the cell current that threatens the reliability of sensing scheme. These issues coupled with continuous increase in the SRAMs size, requires additional techniques and treatments such as read-assist techniques to ensure fast and reliable read operation. In this study, the authors address these concerns and propose a novel read-assist sensing scheme. The circuit is simulated using Spectre in 65 nm CMOS technology. Simulation results showed an increased sensing speed, lower power dissipation and enhanced SRAM dynamic cell stability. A complete comparison is made between the proposed scheme, the conventional circuit and another state of the art design, which shows speed improvement of 55.34, 66.01 and power reduction of 21.33, 89.09 with respect to conventional sense amplifier and the referenced scheme, respectively. These enhancements are at the expense of negligible area overhead. Also, the proposed scheme enables one to reduce the cell s VDD by 227 and 345 mV for the same operating frequency with respect to conventional and referenced circuits, respectively. This results in leakage power reduction of 19.7 and 30 which constitutes a considerable portion of overall power dissipation in nanoscale SRAMs.

Published in:

IET Computers & Digital Techniques  (Volume:6 ,  Issue: 6 )