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Efficient approaches to low-cost high-fault coverage VLSI BIST designs

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1 Author(s)
C. -I. H. Chen ; Dept. of Electr. Eng., Wright State Univ., Dayton, OH, USA

This work introduces a built-in self-test (BIST) design methodology that can sequentially test large very large scale integrated (VLSI) circuits with very high fault coverage. The proposed techniques, circular BIST ((BIST) and (BIST with pseudopartial scan (PPSCAN), are modeled after the principles of the circular self-test path (CSTP). The basis of this method is to trade a minimal increase in hardware overhead for a large increase in fault coverage. It is shown that this technique yields a much higher fault coverage with reasonable time and test vector length when compared with existing sequential test methods. The effectiveness of the technique has been demonstrated by applying it to practical VLSI circuits, which include: 1) the system control coprocessor (CP0) of MIPS 3000 central processing unit (CPU) core and 2) the SIMD graphic engine, namely, enhanced memory chip (EMC). The BIST results show that (BIST and its derivative (BIST with pseudopartial scan (PPSCAN) are feasible for practical VLSI designs and generate BIST with high fault coverage and low overhead

Published in:

IEEE Transactions on Aerospace and Electronic Systems  (Volume:34 ,  Issue: 1 )