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This paper presents a 10-bit, 1MS/s, rail-to-rail successive approximation register analog-to-digital converter (SAR ADC). The ADC uses a bootstrapped sampling switch to achieve better linearity and also adopts a generalized non-binary redundant algorithm and a rail-to-rail dynamic latched comparator to obtain higher Effective Number of Bits (ENOB). This ADC designed and fabricated in 0.18μm CMOS process achieves a signal-to-noise-and-distortion ratio (SNDR) of 58.9dB at 1MS/s which corresponds to an ENOB of 9.5. It also obtains a good linearity (DNL/INL) value of less than ±0.46LSB. At 1.8V supply, the ADC attains a Figure of Merit (FOM) of 181fJ/conversion-step. The ADC also consumes 34.6μW from a 1.2V supply with an ENOB of 8.7 resulting in a FOM of 83fJ/conversion-step.
Date of Conference: 21-23 Nov. 2012