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A 1.1-V 12-bit 20-MS/s pipelined ADC with 1.8-Vpp full-swing in 0.13-μm CMOS

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5 Author(s)
Peiyuan Wan ; Beijing Embedded Syst. Key Lab., Beijing Univ. of Technol., Beijing, China ; Wei Lang ; Rui Jin ; Chi Zhang
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A front-end unity-gain 1-bit flip-around DAC (FADAC) is exploited in a 12-bit opamp-sharing pipelined ADC, allowing a 1.8-Vpp full-swing input at a 1.1-V supply. The high input swing, coupled with a large feedback factor (≈1) of the FADAC, enables a low-voltage low-power design for a high resolution pipelined ADC. The prototype 12-bit ADC operating at 20-MS/s and 1.1-V supply achieves a 66.4 dB SNDR and 76.7 dB SFDR with a 3 MHz input. The ADC consumes 5.2 mW of power and occupies an active area of 0.44 mm2 in 0.13-μm CMOS.

Published in:

Radio-Frequency Integration Technology (RFIT), 2012 IEEE International Symposium on

Date of Conference:

21-23 Nov. 2012

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