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Methodology for fault grading high speed I/O interfaces used in complex Graphics Processing Unit

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5 Author(s)
Khare, A. ; Nvidia Graphics, Bangalore, India ; Kishore, P. ; Reddy, S. ; Rajan, K.
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Graphics Processing Unit (GPU) requires I/O bandwidth of the order of Gbps which can be met by implementation of High Speed Serializer/Deserializer differential I/Os with clock embedded in data stream, traditionally tested using functional Built In Self Test (BIST). Implementation of these I/Os on complex graphics chip poses requirement for fault grading these I/Os. This paper presents the challenges involved in fault grading SerDes I/Os used in Nvidia's GPU chips and proposes methodology for extracting fault coverage numbers using industry standard tools.

Published in:

Test Conference (ITC), 2012 IEEE International

Date of Conference:

5-8 Nov. 2012

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