Design of a fault-tolerant microprocessor: a simulation approach

This paper presents an approach for assessing the merits and the cost of incorporating processor-level error detection and recovery mechanisms. The approach is exemplified by implementing several fault-tolerant mechanisms into a 32-bit, MIPS R3000-compatible, RISC microprocessor and conducting simulation-based fault injection experiments. The mechanisms are triple modular redundancy (TMR), retry on duplication-comparison, and retry on parity-checking codes. Reliability gains and performance/area overheads are quantitatively evaluated for each error-detection/recovery scheme. The fault injection analysis results indicate that the highest fault coverage is achieved with the code-based retry technique.