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Design of a fault-tolerant microprocessor: a simulation approach

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2 Author(s)
Kab Joo Lee ; Samsung Electron. Inc., Kyungkido, South Korea ; G. Choi

This paper presents an approach for assessing the merits and the cost of incorporating processor-level error detection and recovery mechanisms. The approach is exemplified by implementing several fault-tolerant mechanisms into a 32-bit, MIPS R3000-compatible, RISC microprocessor and conducting simulation-based fault injection experiments. The mechanisms are triple modular redundancy (TMR), retry on duplication-comparison, and retry on parity-checking codes. Reliability gains and performance/area overheads are quantitatively evaluated for each error-detection/recovery scheme. The fault injection analysis results indicate that the highest fault coverage is achieved with the code-based retry technique

Published in:

Fault-Tolerant Systems, 1997. Proceedings., Pacific Rim International Symposium on

Date of Conference:

15-16 Dec 1997