Referenced Items are not available for this document.
This paper presents an all-digital technique to modulate the system clock and local clocks in response to global and local voltage noise to prevent timing errors during low-voltage operation. The critical path replica circuits are utilized to change the clock period within a clock cycle in response to transient supply noise. Measurement in 130-nm CMOS demonstrates reliable operation of a test pipeline over a wide dc (1.3-0.74 V) voltage range. At 0.81 V, the pipeline operates without timing errors at 7.2% higher frequency even under a 189-mV transient voltage droop.
Published in:
Circuits and Systems II: Express Briefs, IEEE Transactions on
(Volume:59
,
Issue:
12
)
Date of Publication: Dec. 2012
- Page(s):
- 893 - 897
- ISSN :
- 1549-7747
- INSPEC Accession Number:
- 13270804
- Digital Object Identifier :
- 10.1109/TCSII.2012.2231033
- Date of Publication :
- 01 January 2013
- Date of Current Version :
- 01 February 2013
- Issue Date :
- Dec. 2012
- Sponsored by :
- IEEE Circuits and Systems Society
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