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This paper presents an all-digital technique to modulate the system clock and local clocks in response to global and local voltage noise to prevent timing errors during low-voltage operation. The critical path replica circuits are utilized to change the clock period within a clock cycle in response to transient supply noise. Measurement in 130-nm CMOS demonstrates reliable operation of a test pipeline over a wide dc (1.3-0.74 V) voltage range. At 0.81 V, the pipeline operates without timing errors at 7.2% higher frequency even under a 189-mV transient voltage droop.
Circuits and Systems II: Express Briefs, IEEE Transactions on (Volume:59 , Issue: 12 )
Date of Publication: Dec. 2012