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This paper proposes a novel adaptive voltage scaling low power design methodology for large System on Chip (SoC) that demands constant data throughput. The proposed technique scales the supply voltage to the SoC based on operating conditions and bit error rate (BER) margin available in a system. It allows occasional timing errors in the circuit and relies on a forward error correction (FEC) that exists in the system to correct the errors. As a result, the proposed technique requires no hardware overhead but yields significant power savings. More importantly, it does not require any circuit modification based on place and route, thus easy to implement and has no impact on time to market. The new technique has been implemented in a complex telecom SoC design and silicon measurement shows power savings up to 46%.