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Optimal power-constrained SoC test schedules with customizable clock rates

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3 Author(s)
Vijay Sheshadri ; Department of Electrical and Computer Engineering, Auburn University, Auburn, AL 36849 ; Vishwani D. Agrawal ; Prathima Agrawal

In this paper, we propose a method of minimizing test time in SoCs (System-on-chip), for a given power budget, by varying the test clock frequency for each test session. Since frequency is proportional to the test time and the power dissipated, by controlling the test clock frequency, the power dissipated and the test time per session can be adjusted so as to yield an optimal solution to the test scheduling problem. To achieve this, we modify the existing ILP (Integer-Linear Program) model for optimal test scheduling to include a variable frequency parameter which, in turn, controls the test time and power. For the optimization, we have used an open-source ILP solver. We also prove that the lower bound on the total test time of an SoC, is obtained by executing individual cores (tests) per session at their maximum frequency of operation, such that their test power is same as the power budget. Results show an improvement of 27% over existing solution for the benchmark SoC, ASIC Z.

Published in:

SOC Conference (SOCC), 2012 IEEE International

Date of Conference:

12-14 Sept. 2012