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A 55nm 0.5V 128Kb cross-point 8T SRAM with data-aware dynamic supply Write-assist

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13 Author(s)
Yung-Wei Lin ; Dept. of Electron. Eng., Nat. Chiao-Tung Univ., Hsinchu, Taiwan ; Hao-I. Yang ; Mao-Chih Hsia ; Yi-Wei Lin
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This paper describes an area-efficient variation-tolerant data-aware dynamic supply Write-assist scheme for a cross-point 8T SRAM. A 128Kb test chip implemented in 55nm Standard Performance CMOS technology achieves error free full functionality without redundancy from 1.5V down to 0.5V, with area overhead of only 0.834% for the Data-Aware Write-Assist (DAWA). The superiority of the proposed scheme in area overhead and improvement in Write VMIN and Write bit failure rate are demonstrated via comparison of measurement results with that from a base 128Kb design with Negative Bit-Line (NBL) Write-assist scheme. The maximum operating frequency is 494MHz (271MHz) at 0.6V (0.5V).

Published in:

SOC Conference (SOCC), 2012 IEEE International

Date of Conference:

12-14 Sept. 2012