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A low power high speed dual data rate acquisition system using FPGA

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1 Author(s)
Abhishek Tiwari ; Broadcast and Communications Group, CDAC, Thiruvananthapuram, India

Nowadays high speed Data Converters are increasingly needed and much sought after. An application involving high-speed data acquisition systems puts pressure on the analog to digital interface data rate also. The high sampling rate of the Analog to Digital Converters (ADC) demands the use of advanced acquisition techniques as well as the latest technology available. The purpose of this paper is to present a practical approach for interfacing Field Programmable Gate Array (FPGA) with a high speed dual data rate (DDR) Analog to Digital Converter which performs digitization of the input signal with a sampling rate of 200 MSPS or higher. The technique described here captures the digitized ADC samples at both rising and falling edges of the sampling clock using dedicated ILOGIC resources in FPGA. The main advantages of such an approach compared to other existing designs are: accurate clock to data alignment on all channels without using any internal DLL or global clock networks. The technique has the added advantage of low power and resources consumption. In this paper we present the details of the proposed method in which an FPGA is used to collect data from 8 bit pairs of LVDS compatible ADC channels clocked with Dual Data rate at 200 MSPS. The proposed method of implementation can be used as a front-end for a wide range of high speed applications.

Published in:

Communication, Information & Computing Technology (ICCICT), 2012 International Conference on

Date of Conference:

19-20 Oct. 2012