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In this study an ultra-low-power successive approximation register (SAR) analogue-to-digital converter (ADC) for radio frequency identification (RFID) applications is presented. Several techniques are used to further reduce power consumption and relatively elevate the speed of the conventional SAR ADC. These techniques include a low-power comparator with no static current, a dual-stage (resistor-string/capacitive dividing) architecture as digital-to-analogue converter (DAC), and utilising low-power design with the aid of low supply voltages: 0.7 V for DAC, and 0.5 V for SAR block and pulse generator circuitry (PGC). In the DAC architecture fine search will be performed by only two C and 15C capacitors which reduce the silicon area significantly. The circuit designed in 0.18 m complementary metal-oxide-semiconductor (CMOS), technology and post-layout simulations show that the 8-bit core ADC consumes almost 78.4 nW at 17.8 kS/s speed whereas the PGC block consumes 84.1 nW. The results show that the proposed ADC has higher speed with almost the same power consumption in comparison to its charge redistribution counterparts.