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Scan latch design for delay test

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1 Author(s)
Savir, J. ; Dept. of Electr. & Comput. Eng., New Jersey Inst. of Technol., Newark, NJ, USA

This paper describes three new designs of a shift register latch that lend themselves to distributed self-test and delay test. The advantages of these new SRLs are faster application of test vectors, higher DC and AC fault coverages, with low performance impact. Operation, cost, and other attributes are studied in detail. Results of adopting one of the new SRLs are reported on three pilot chips

Published in:

Test Conference, 1997. Proceedings., International

Date of Conference:

1-6 Nov 1997