A symbolic simulation-based ANSI/IEEE Std 1149.1 compliance checker and BSDL generator

The paper shows how to extract the boundary-scan circuitry from an IC (Integrated Circuit), verify its compliance to IEEE Std 1149.1 and generate its BSDL (Boundary Scan Description Language) description. This work applies to the 75% of boundary-scan ICs that have hand-generated or macro-cell based boundary-scan circuity. It also applies to boundary-scan ICs designed using RTL (Register Transfer Level) synthesis.