Test Case Generation from UML State Machine Diagram: A Survey

UML is widely accepted and practiced in industries for modeling and design of software systems. Software requirements and design are very important parts of software development, which must be validated and verified before implementation. UML State Machine diagram is an important formalism to model the dynamics of the system. In this paper, a comparative study of the test case generation techniques from UML State Machine diagram has been done. This study is an attempt to find out the work that has already been done in this field and various aspects of UML state machines that have been considered for generating test cases. Finally, this paper presents a scope to generate test data for complex state machine involving concurrent states and events.