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NROM is one of the emerging non-volatile-memory technologies, which provides very high data density, low fabrication cost, and better value stability. It is also promising for replacing current floating-gate-based non-volatile memory such as flash memory. In order to raise the fabrication yield and enhance its reliability, a novel test and repair flow is proposed in this paper. Instead of the traditional fault replacement techniques, fault masking techniques are also exploited by considering the logical effects of physical defects when the customer's code is to be programmed. Two techniques are exploited to maximize the possibilities of fault masking-address scrambling and data inversion. Graph models are also proposed for modeling these methods. The proposed methods can be easily incorporated into the ROM BIST architectures. According to experimental results, the fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.