An Effective At-Speed Scan Testing Approach Using Multiple-Timing Clock Waveforms

Today, at-speed test cost comprises a majority of the total test cost of a design. This derives from the fact that if the design has numerous data transfers between clock domains, we must generate test patterns for all of the synchronous data transfers to guarantee high reliability. Conventionally, at-speed test patterns are generated for each of the transfers separately. In order to reduce at-speed test application time, we take an approach to increase the number of the transfers tested concurrently. Evaluation results show that our approach is effective for that purpose.