Skip to Main Content
I have had several lucky breaks in my career. One of them was the opportunity to be immersed in the emergence of VLSI technology and its associated design methodology. I got my Ph.D. in Experimental Physics from the University of Basel, Switzerland, in 1969. My first job was with Bell Telephone Laboratories in Murray Hill, New Jersey. Because of my thesis, in which I studied the behavior of Interface States in Metal-Oxide-Semiconductor Field-Effect Transistors, I was placed into Lab 225, which was engaged in building solid state imaging devices based on the brand new CCD (Charge-Coupled Device) technology, which had been conceived there a few months earlier. When I arrived, the group with Mike Tompsett and Gil Amelio had just demonstrated a CCD sensor array with 8 by 8 pixels. Since I have been enamored with geometry ever since high-school, I jumped to the opportunity to design the layouts of much larger imaging arrays, first with 128 by 128 pixels, and eventually (in 1973) with two interlaced fields of 256 scan lines, which was compatible with the American broadcast TV format. The latter device was way larger than any other IC chips of that time: It had ¾ of a million MOS electrodes placed in a rectangle measuring ½ inch by 5/8 of an inch (Figure 1).