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Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature

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8 Author(s)
Takahashi, R. ; Inst. of Ind. Sci., Univ. of Tokyo, Tokyo, Japan ; Takata, H. ; Yasufuku, T. ; Fuketa, H.
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Temperature dependence of 256 within-die random gate delay variations in sub-threshold logic circuits is measured in 40-nm CMOS test chips. When the temperature is reduced from 25 °C to -40°C, the sigma/average (σ/μ) of the gate delay at 0.3 V increases by 1.4 times. A newly developed model shows that σ/μ of the gate delay is proportional to 1/T for the first time, where T is the absolute temperature.

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Circuits and Systems II: Express Briefs, IEEE Transactions on  (Volume:59 ,  Issue: 12 )