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Silicon tunneling field-effect transistors with tunneling in line with the gate field

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8 Author(s)
Fischer, I.A. ; Inst. for Semicond. Eng., Univ. of Stuttgart, Stuttgart, Germany ; Bakibillah, A.S.M. ; Golve, M. ; Hahnel, D.
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We present experimental results on the fabrication and characterization of vertical Si tunneling field-effect transistors (TFETs) in a device geometry with tunneling in line with the gate field. Compared to vertical Si TFETs without this geometry modification, on-currents are increased by more than one order of magnitude with ION = 1.1 μA/μm at VDS = 0.5 V and an ION/IOFF ratio of 3.4 ·104 in n-channel operation. We present further suggestions for device improvements.

Published in:

Electron Device Letters, IEEE  (Volume:34 ,  Issue: 2 )

Date of Publication:

Feb. 2013

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