Cart (Loading....) | Create Account
Close category search window
 

Silicon tunneling field-effect transistors with tunneling in line with the gate field

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

8 Author(s)
Fischer, I.A. ; Inst. for Semicond. Eng., Univ. of Stuttgart, Stuttgart, Germany ; Bakibillah, A.S.M. ; Golve, M. ; Hahnel, D.
more authors

We present experimental results on the fabrication and characterization of vertical Si tunneling field-effect transistors (TFETs) in a device geometry with tunneling in line with the gate field. Compared to vertical Si TFETs without this geometry modification, on-currents are increased by more than one order of magnitude with ION = 1.1 μA/μm at VDS = 0.5 V and an ION/IOFF ratio of 3.4 ·104 in n-channel operation. We present further suggestions for device improvements.

Published in:

Electron Device Letters, IEEE  (Volume:34 ,  Issue: 2 )

Date of Publication:

Feb. 2013

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.