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Process-Resilient Low-Jitter All-Digital PLL via Smooth Code-Jumping

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5 Author(s)
Pei-Ying Chao ; Electr. Eng. Dept., Nat. TsingHua Univ., Hsinchu, Taiwan ; Chao-Wen Tzeng ; Shi-Yu Huang ; Chia-Chieh Weng
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For an all-digital phase-locked loop, the frequency range supported is often segmented, and this could cause significant jitter when the operating condition (such as the supply voltage and/or the temperature) changes. To address this issue, we present a scheme, called smooth code-jumping, that can stitch together the segmented frequency profile of a digitally controlled oscillator (DCO) into a continuous range, and thereby reduce the jitter significantly. This scheme incorporates a new mirror-DCO-based calibration scheme to take into account process variations. We validate this scheme by test chips in 0.18-μm CMOS technology. Measurement results show that, when operating at 1 GHz, the rms jitter is 4.3 ps (0.43%UI) and the peak-to-peak jitter is 35.6 ps (3.56%UI), respectively.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 12 )