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Cell-Based Process Resilient Multiphase Clock Generation

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3 Author(s)
Ruo-Ting Ding ; Electr. Eng. Dept., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Shi-Yu Huang ; Chao-Wen Tzeng

Multiphase clock generation (MPCG) is a problem that aims to generate a sequence of clock signals with the same frequency and uniformly shifted phases. In this brief, we present a cell-based MPCG design with two technical merits. We use a process calibration scheme that makes the per-phase delay (defined as the timing difference between two consecutive phases of clock signals) highly accurate. We further exploit a so-called cyclic property to make the achievable per-phase delay much smaller than a buffer delay. A design with 16-phase clock signal (with the per-phase delay of only 100 ps) is used to demonstrate its effectiveness.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:21 ,  Issue: 12 )