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End-to-end delay is an important metric in Network-on-Chip (NoC) performance evaluation. Two kinds of approaches often utilized for evaluating the end-to-end delay of NoC are discrete-event simulation and theoretical analysis. The former one is widely used due to its high accuracy, but it's extremely slow while performing large-scale NoC design space exploration. The later one is more efficient in fast performance evaluation. In this paper, we propose a max-plus algebra based NoC delay estimation approach, which can be used as an effective NoC design tool to estimate the end-to-end packet/flit delay. The proposal has no assumptions on the NoC topology, traffic pattern and hardware implementation methodologies, which makes it very attractive for fast performance evaluation. Experimental results show the fitness of our approach.