Referenced Items are not available for this document.
Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation
Published in:
Wafer Scale Integration, 1990. Proceedings., [2nd] International Conference on
Date of Conference: 23-25 Jan 1990
- Page(s):
- 203 - 211
- Meeting Date :
- 23 Jan 1990-25 Jan 1990
- Print ISBN:
- 0-8186-9013-5
- INSPEC Accession Number:
- 3763916
- Conference Location :
- San Francisco, CA
- Digital Object Identifier :
- 10.1109/ICWSI.1990.63902
- Product Type:
- Conference Publications
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