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This paper presents the optimization of the current control loop implemented in a field programmable gate array (FPGA) based inverter. The bandwidth of the current controller is significantly enhanced by reducing the delay times to its theoretical minimum. The optimizations are at first analyzed on a theoretical basis and afterwards verified on the actual target system. It is discussed, that the optimized current controller can be implemented without any drawbacks in terms of available output voltage. It is shown, that the significant reduction of delay times can be implemented in practice, greatly enhancing the bandwidth of the current controller, thus allowing a much higher controller gain.