By Topic

Encoder implementation with fpga for non-binary LDPC codes

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Weigang Chen ; School of Electronic Information Engineering, Tianjin University, 300072, China ; Chenchi Liang ; Tai Guo ; Yao Ding

Low-complexity encoders for non-binary low-density parity-check (LDPC) codes with code rate of 1/3 are implemented with Field Programmable Gate Arrays. In this design, the locations of non-zero entries in the parity-check matrix are generated on the fly with several integers called address generators. Furthermore, the non-zero entries are limited to only a pair of permuted elements and thus a single bit is used to choose the different constant coefficient multipliers rather than using the general multipliers in Galois fields. In this way, efficient encoders are implemented using only several constant-coefficient multipliers and limited memories for a type of non-binary LDPC codes, which show significant error correction performance when the code length is large.

Published in:

2012 18th Asia-Pacific Conference on Communications (APCC)

Date of Conference:

15-17 Oct. 2012