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Encoder implementation with fpga for non-binary LDPC codes

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4 Author(s)
Weigang Chen ; Sch. of Electron. Inf. Eng., Tianjin Univ., Tianjin, China ; Chenchi Liang ; Tai Guo ; Yao Ding

Low-complexity encoders for non-binary low-density parity-check (LDPC) codes with code rate of 1/3 are implemented with Field Programmable Gate Arrays. In this design, the locations of non-zero entries in the parity-check matrix are generated on the fly with several integers called address generators. Furthermore, the non-zero entries are limited to only a pair of permuted elements and thus a single bit is used to choose the different constant coefficient multipliers rather than using the general multipliers in Galois fields. In this way, efficient encoders are implemented using only several constant-coefficient multipliers and limited memories for a type of non-binary LDPC codes, which show significant error correction performance when the code length is large.

Published in:

Communications (APCC), 2012 18th Asia-Pacific Conference on

Date of Conference:

15-17 Oct. 2012

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