Cart (Loading....) | Create Account
Close category search window
 

Resource Allocation and Design Techniques of Prebond Testable 3-D Clock Tree

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tak-Yung Kim ; Syst. LSI Bus. Unit, Samsung Electron. Co., Ltd., Yongin, South Korea ; Taewhan Kim

In 3-D stacked integrated circuit (IC) manufacturing, for the acceptable high yield, it is essential to stack only known good dies by testing the individual dies at the prebond stage. While the postbonded 3-D IC is operated by a low power 3-D clock tree, the prebond testing requires a 2-D clock tree on each die. The previous work provided a prebond testable 3-D clock tree synthesis solution by allocating through-silicon via (TSV) buffers and redundant trees with transmission gates. However, no optimizations on the allocation and design of the resources have been addressed. In this paper, we propose practically viable clock tree optimization techniques under prebond testability: 1) TSV-buffer-aware topology generation techniques that enable an economical buffer allocation by preventing (potentially “bad”) TSV buffers; 2) delay-locked loop (DLL)-based 2-D clock network design method that offers a diverse exploration of 2-D clock tree synthesis and resource allocation for prebond die testing; and 3) a new circuit design technique of transmission gates that completely removes its control line. Compared to the existing topology generation algorithms, our proposed TSV-buffer-aware topology generation uses 68%-88% fewer TSVs, 36%-58% less wire resource, and 35%-69% fewer buffers while consuming 17%-43% less clock power for the benchmark circuits, and our proposed method of clock tree exploration provides many alternative structures of a 2-D clock tree, considering the resource balance between DLLs and wires. In addition, the use of our self-controlled clock transmission gate enables a drastic reduction of the total wirelength, which amounts to 18% on average.

Published in:

Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on  (Volume:32 ,  Issue: 1 )

Date of Publication:

Jan. 2013

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.