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Triple-Gate FinFETs have been demonstrated to be promising to push further the down scaling of CMOS technology, because of their high immunity against the so-called short channel effects. However, due to their three-dimensional (3-D) architecture, strong degradation of their analog characteristics has been reported, basically due to large extrinsic resistances and capacitances. In this paper, based on measurements and 3-D numerical simulations, we analyze the impact of the extrinsic gate capacitances on the RF behavior of FinFETs. It is shown that the reduction of the fin spacing, the modification of the fin geometrical aspect ratio (height/width) as well as the optimization of the fin spacing-fin Source/Drain extension ratio can significantly improve the FinFET RF performance.