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RegularRoute: An Efficient Detailed Router Applying Regular Routing Patterns

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2 Author(s)
Yanheng Zhang ; Department of Electrical and Computer Engineering, Iowa State Unviersity, Ames, IA, USA ; Chris Chu

In this paper, we propose RegularRoute, an efficient detailed router encouraging regular routing patterns. RegularRoute is proposed for potentially better design rule satisfaction based on a correct-by-construction methodology. Given the underlying spacing-based design rules, 2-D global routing solution, and 3-D detailed routing tracks, RegularRoute generates a 3-D detailed routing solution in a bottom-up layer-by-layer framework. At the beginning, local nets, i.e., nets or subnets that are inside one G-cell, are routed using vertical spine routing topology. Routing usage of local nets is treated as blockage when assigning global segments. Then, for each layer we formulate the problem of global segment assignment inside each panel, i.e., grouped routing tracks, as a maximum weighted independent set (MWIS) problem. We propose a fast and effective heuristic to solve the MWIS problem. Unassigned segments are partially routed by a greedy technique. For the unrouted portion of each segment, its terminals are promoted so that the assignment is deferred to the upper layers. At the top layers, we apply the panel merging and maze routing techniques to improve routability. RegularRoute generates a detailed routing solution that satisfies the basic spacing-based design rules. To satisfy all the design rules, we propose an abstract idea of local optimization based on local shift and rip-up-and-reroute, assuming that most design rules are complex functions of local and neighboring geometries. Because of the unavailability of proper academic grid-based detailed routing benchmarks, we propose two sets of detailed routing test cases derived from ISPD98 and ISPD05/06 placement benchmark suites, respectively. Our experimental results demonstrate the effectiveness and efficiency of RegularRoute.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:21 ,  Issue: 9 )