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Efficient parametric yield estimation of analog/mixed-signal circuits via Bayesian model fusion

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5 Author(s)
Xin Li ; Carnegie Mellon Univ., Pittsburgh, PA, USA ; Wangyang Zhang ; Fa Wang ; Shupeng Sun
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Parametric yield estimation is one of the most critical-yet-challenging tasks for designing and verifying nanoscale analog and mixed-signal circuits. In this paper, we propose a novel Bayesian model fusion (BMF) technique for efficient parametric yield estimation. Our key idea is to borrow the simulation data from an early stage (e.g., schematic-level simulation) to efficiently estimate the performance distributions at a late stage (e.g., post-layout simulation). BMF statistically models the correlation between early-stage and late-stage performance distributions by Bayesian inference. In addition, a convex optimization is formulated to solve the unknown late-stage performance distributions both accurately and robustly. Several circuit examples designed in a commercial 32 nm CMOS process demonstrate that the proposed BMF technique achieves up to 3.75× runtime speedup over the traditional kernel estimation method.

Published in:

Computer-Aided Design (ICCAD), 2012 IEEE/ACM International Conference on

Date of Conference:

5-8 Nov. 2012