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Programmable routers for efficient mapping of applications onto NoC-based MPSoCs

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6 Author(s)

We extend the state-of-the-art DSPIN network-on-chip architecture by defining programmable NoC routers that can establish effective static scheduling and routing of data packets as demanded by the application. Router programs are the result of a general compilation process which targets the NoC and the computing cores altogether. The objective is to reduce NoC contentions, improving speed and timing predictability. We consider the range of applications of such an approach and provide results on two of them (a simple embedded controller and an FFT).

Published in:

Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on

Date of Conference:

23-25 Oct. 2012