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HLS-based fast design space exploration of ad hoc hardware accelerators: A key tool for MPSoC synthesis on FPGA

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5 Author(s)
Youenn Corre ; Lab-STICC, Université de Bretagne Sud, 56100 Lorient, France ; Van-Trinh Hoang ; Jean-Philippe Diguet ; Dominique Heller
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Over the last decade many academic and industrial system synthesis and codesign tools have been proposed to designers. However most of these tools are based on IP Libraries but either these libraries are incomplete or are simply not adapted to the targets and constraints. It means that something important is missing when it comes to real implementations. We address this question in this paper and propose a flexible, fast and practical solution. We use high level synthesis (HLS) to obtain fast estimations of hardware accelerators that can then be embedded within the loop of a larger design space exploration flow. Once some solutions are selected they can be directly reuse to synthesise and produce real IPs. In this paper we present the approach and the tool as a key component of our heterogeneous multiprocessor synthesis framework.

Published in:

Design and Architectures for Signal and Image Processing (DASIP), 2012 Conference on

Date of Conference:

23-25 Oct. 2012