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Design-Aware Defect-Avoidance Floorplanning of EUV Masks

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2 Author(s)
Kagalwalla, A.A. ; Dept. of Electr. Eng., Univ. of California, Los Angeles, Los Angeles, CA, USA ; Gupta, P.

Fabricating defect-free mask blanks remains a major obstacle for the adoption of EUV lithography. We propose a simulated annealing based gridded floorplanner for single-project multiple-die reticles that minimize the design impact of buried defects. Our results show a substantial improvement in mask yield with this approach. For a 60-defect mask, our approach can improve the mask yield from 0% to 26%. If additional design information is available, it can be exploited for more accurate yield computation and further improvement in mask yield to 99.6%. These improvements are achieved with a limited area overhead of less than 0.2% on the exposure field. Our simulation results also indicate that around 10%-30% mask yield improvement is possible as a result of floorplanning compared to shifting the entire mask pattern. Our floorplanner can tolerate a defect position error (due to mask blank inspection tools) of 0.25 μm with just a 2% reduction in yield. The impact of defect dimensions and multilayer EUV patterning on the viability of floorplanning is also analyzed in this paper.

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Semiconductor Manufacturing, IEEE Transactions on  (Volume:26 ,  Issue: 1 )