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On the Impact of Through-Silicon-Via-Induced Stress on 65-nm CMOS Devices

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7 Author(s)
Roshan Weerasekera ; Institute of Microelectronics, A*STAR (Agency for Science, Technology and Research), Singapore ; Hong Yu Li ; Lim Wei Yi ; Hu Sanming
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Electrical evaluation of the impact of through-silicon via (TSV)-induced stress on 65-nm MOSFETs is presented in this letter. MOSFETs with varying widths and lengths were laid out at a minimum distance of 1.2 up to 16 μm from TSVs at different orientations. The TSV diameter, height, and dielectric barrier thickness are 8, 60, and 1 μm, respectively. Measured change of saturation current (Ion) of devices at the minimum distance is less than 4% for all the cases. The reliability of the devices was also investigated up to 1000 thermal cycles, between -55°C and 125 °C. No significant change in MOSFET performance is observed in comparison with the measurements before thermal cycling.

Published in:

IEEE Electron Device Letters  (Volume:34 ,  Issue: 1 )