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Automatic congestion detection in MPSoC programs using data mining on simulation traces

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3 Author(s)
Sofiane Lagraa ; LIG, CNRS/Grenoble-INP/UJF ; Alexandre Termier ; Frédéric Pétrot

The efficient deployment of parallel software, specifically legacy one, on Multiprocessor systems on chip (MPSoC) is a challenging task. In this paper, we introduce the use of a data-mining approach on traces of a functionally correct program to automatically identify recurring congestion points and their sources. Each memory transaction, i.e. instruction fetch, data load and data store, occurring in the system is logged, thanks to the use of a virtual platform of the system. The resulting trace is analyzed to discover memory access patterns that are occurring frequently and that feature high latencies. These patterns are sorted by order of decreasing occurrence and estimated congestion level, allowing the easy identification of the sources of inefficiency. We have simulated a MPSoC with 16 processors running multiple applications, and have been able to automatically detect congestion on resources and their sources in the parallel program using this technique by analyzing gigabytes of traces.

Published in:

2012 23rd IEEE International Symposium on Rapid System Prototyping (RSP)

Date of Conference:

11-12 Oct. 2012