Skip to Main Content
Device-level variability in silicon double-gate lateral tunnel field-effect transistors (TFETs) due to line-edge roughness (LER) and random dopant fluctuation (RDF) is investigated for designs with a 20-nm gate length and body widths of 5 or 10 nm (“20/5” and “20/10,” respectively). Variability in TFET threshold voltage (VT), on-state drive current (Ion), off-state leakage current (Ioff), and subthreshold swing is examined by means of statistical technology computer-aided design simulations with consideration of body LER up to 1 nm in amplitude as well as RDF for body heights ranging from 10 to 40 nm. The effects of body LER and RDF are found to be similar in magnitude and also comparable to those in similarly designed fin FETs, with the exception of Ion variability which is roughly three times higher for TFETs. Arguments are presented to explain these findings based on the operating principle of TFETs compared to standard metal-oxide-semiconductor-FET-based technology.