Skip to Main Content
This paper introduces a maximum-gain ring oscillator (MGRO) topology that maximizes the power gain (PG) achieved by the active devices in a ring oscillator using appropriately designed passive matching networks to maximize the frequency of oscillation. A design methodology is provided along with expressions for the passive matching elements. In the absence of passive losses, the topology can oscillate at the fmax of the active devices. In the presence of passive loss, for the first time, the losses can be taken into account in a closed-form fashion to maximize device PG, and consequently, oscillation frequency. Based on this topology, two different oscillators operating at approximately 108 and 158 GHz are implemented using the 56-nm body-contacted devices (fmax ≈ 200 GHz) of IBM's 45-nm silicon-on-insulator CMOS technology. The fact that these two oscillators function well with marginal startup gains of 2.62 and 0.62 dB, respectively, demonstrates the robustness of the techniques described here. The second harmonic of the oscillation is extracted using a load-pull-optimized extraction network. This topology can be generalized for the extraction of any harmonic from MGROs with a different number of stages. The oscillators generate -14.4 dBm at 216.2 GHz and -21 dBm at 316.5 GHz while drawing 57.5 and 46.4 mW of dc power, respectively. This paper also describes the modeling of CMOS active and passive devices for high millimeter-wave and sub-millimeter-wave integrated-circuit design.