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FPGA implementation of LDPC encoder with approximate lower triangular matrix

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3 Author(s)
Yi Hua Chen ; Oriental Inst. of Technol., Inst. of Inf. & Commun. Eng., Taipei, Taiwan ; Jue Hsuan Hsiao ; Jheng Shyuan He

This study used the weight (3, 6) approximate lower triangular regular parity check matrix to implement the LDPC encoding on the 5641R FPGA of the Software Define Radio system developed by National Instruments (NI) [1]. This study provided a detailed introduction to the encoding mechanism of the approximate lower triangular LDPC, and completed the implementation and verification of FPGA hardware.

Published in:

Consumer Electronics (GCCE), 2012 IEEE 1st Global Conference on

Date of Conference:

2-5 Oct. 2012