Referenced Items are not available for this document.
Reliability issues are increasingly problematic as technology scales down and the supply voltage is lowered. Specifically, the Soft-Error Rate (SER) increases due to the reduced feature size and the reduced charge. This paper describes an adaptive method to lower memory power using a dual Vdd in a column-based Vdd memory with Built-in Current Sensors (BICS). Using our method, we reduce the memory power by about 40% and increase the error immunity of the memory without the significant power overhead as in previous methods.
Published in:
VLSI and System-on-Chip (VLSI-SoC), 2012 IEEE/IFIP 20th International Conference on
Date of Conference: 7-10 Oct. 2012
- Page(s):
- 207 - 212
- E-ISBN :
- 978-1-4673-2656-8
- Print ISBN:
- 978-1-4673-2657-5
- INSPEC Accession Number:
- 13187422
- Conference Location :
- Santa Cruz, CA
- Digital Object Identifier :
- 10.1109/VLSI-SoC.2012.6379031
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